代码搜索：complement
找到约 1,455 项符合「complement」的源代码
代码结果 1,455
www.eeworm.com/read/478303/6714498
vhd ex_p5_13_complementer.vhd
entity xor2 is
port(i1,i2: in BIT ;o : out BIT) ;
end xor2;
architecture DF of xor2 is
begin
o
www.eeworm.com/read/403933/11498604
html help.if-less.html
Instruction : if-less
if-less
This instruction compares the ?BX? register to its
www.eeworm.com/read/341752/12067594
_h stdtypes._h
#ifndef _STDTYPES_H
#define _STDTYPES_H
/*
********************************************************************
*
* (c)Copyright Injectronix
*
* The existence and contents of this docume
www.eeworm.com/read/413826/11140753
hwl c_layout.hwl
OPEN source 0 0 50 33
Source:1 < attributes SHOW_CORE 0,TOOLTIP on,TOOLTIP_FORMAT signed,TOOLTIP_MODE details,FREEZE off,MARKS on
OPEN source 50 0 50 33
Source:2 < attributes SHOW_CORE 1,TOOLTIP on
www.eeworm.com/read/103915/15716302
c infuncmp.c
//
// infuncmp.c
//
// Decodes uncompressed blocks
//
#include "inflate.h"
#include "infmacro.h"
//
// Returns whether there are >= n valid bits in the bit buffer
//
#define ASSERT_BITS_
www.eeworm.com/read/378278/9238570
vhd absval.vhd
-------------------------------------------------------------------------------
-- Title : Absolute value for 2's complement numbers
-- Project : VHDL Library of Arithmetic Units
-----------
www.eeworm.com/read/176101/9516412
vhd absval.vhd
-------------------------------------------------------------------------------
-- Title : Absolute value for 2's complement numbers
-- Project : VHDL Library of Arithmetic Units
-----------
www.eeworm.com/read/176100/9516557
vhd absval.vhd
-------------------------------------------------------------------------------
-- Title : Absolute value for 2's complement numbers
-- Project : VHDL Library of Arithmetic Units
-----------
www.eeworm.com/read/271050/11010752
pkg std_logic_class.pkg
-- +------------------------------------
-- | Library: VFP
-- | Designer: Tim Pagden
-- | Opened: 25 Nov 1992
-- +------------------------------------
library IEEE;
package std_logic_class i
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vhd 二進位3-bit補述產生器.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--D Flip-Flop
entity dff is
port(CLK, RESET, D : in std_logic;
Q :