absval.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Absolute value for 2's complement numbers
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AbsVal.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/06
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Computes the absolute value using a parallel-prefix 2's complementer.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AbsVal is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
	Z : out std_logic_vector(width-1 downto 0));  -- result

end AbsVal;

-------------------------------------------------------------------------------

architecture Behavioral of AbsVal is

  signal Asgn, Zsgn : signed(width-1 downto 0);  -- signed

begin

  -- type conversion: std_logic_vector -> signed
  Asgn <= signed(A);

  -- complement if A negative
  Zsgn <= 0 - Asgn when Asgn < 0 else
	  Asgn;

  -- type conversion: signed -> std_logic_vector
  Z <= std_logic_vector(Zsgn);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AbsVal is 

  signal Neg : std_logic;  		-- negation enable
  signal AI : std_logic_vector(width downto 0);  -- A inverted
  signal PO : std_logic_vector(width downto 0);  -- prefix propagate out

begin

  -- negation enable is sign (MSB) of A
  Neg <= A(width-1);
	 
  -- invert A for complement and attach carry-in
  AI <= (A xor (width-1 downto 0 => Neg)) & Neg;

  -- calculate prefix output propagate signal
  prefix : PrefixAnd
    generic map (width+1, speed)
    port map (AI, PO);

  -- calculate result bits
  Z <= AI(width downto 1) xor PO(width-1 downto 0);

end Structural;

-------------------------------------------------------------------------------