代码搜索：combinatorial
找到约 224 项符合「combinatorial」的源代码
代码结果 224
www.eeworm.com/read/445908/7588281
mrp emif_com_map.mrp
Release 9.1i Map J.30
Xilinx Mapping Report File for Design 'EMIF_COM'
Design Information
------------------
Command Line : D:\EDA\Xilinx91i\bin\nt\map.exe -ise
E:/ISE_Prj/EMIF_COM/EMIF_COM.ise -i
www.eeworm.com/read/445908/7588286
drc emif_com.drc
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_MEMORY_15_2_4_0_a2 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data i
www.eeworm.com/read/314805/13558704
bgn alu.bgn
Release 6.2i - Bitgen G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Loading device database for application Bitgen from file "alu.ncd".
"alu" is an NCD, version 2.38, device xcv2
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drc alu.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0011 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the fl
www.eeworm.com/read/481836/6631514
bgn seg.bgn
Release 8.1i - Bitgen I.24
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '2v1000.nph' in environment
D:\Xilinx.
"seg" is an NCD, ver
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drc seg.drc
WARNING:PhysDesignRules:372 - Gated clock. Clock net minute10 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-f
www.eeworm.com/read/155883/11840783
drc segment_scan_clock_24.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0030 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the fl
www.eeworm.com/read/341841/12058248
drc clockcore.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net daycbuf is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the f