clockcore.drc

来自「一个在Xilinx spartan3实现的时钟」· DRC 代码 · 共 33 行

DRC
33 行
字号 
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net daycbuf is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:367 - Netcheck: Loadless. Net day_0__n0001<3> has no load.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y2buf is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y3buf is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y4buf is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net hclkbuf is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0144 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net sclkbuf is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net mclkbuf is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net moncbuf is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y1buf is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.DRC detected 0 errors and 11 warnings.

clockcore.drc - 源码说明

本页面展示了「一个在Xilinx spartan3实现的时钟」中的 clockcore.drc 源码文件，采用 DRC 编程语言编写，共 33 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫开发者社区收录了大量与时钟相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?