emif_com_map.mrp

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

Release 9.1i Map J.30
Xilinx Mapping Report File for Design 'EMIF_COM'

Design Information
------------------
Command Line   : D:\EDA\Xilinx91i\bin\nt\map.exe -ise
E:/ISE_Prj/EMIF_COM/EMIF_COM.ise -intstyle ise -p xc2s200-pq208-5 -cm area -pr b
-k 4 -c 100 -tx off -o EMIF_COM_map.ncd EMIF_COM.ngd EMIF_COM.pcf 
Target Device  : xc2s200
Target Package : pq208
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.36 $
Mapped Date    : Fri Mar 27 16:58:44 2009

Design Summary
--------------
Number of errors:      0
Number of warnings:   32
Logic Utilization:
  Number of Slice Latches:          272 out of  4,704    5%
  Number of 4 input LUTs:           166 out of  4,704    3%
Logic Distribution:
    Number of occupied Slices:                         214 out of  2,352    9%
    Number of Slices containing only related logic:    214 out of    214  100%
    Number of Slices containing unrelated logic:         0 out of    214    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          181 out of  4,704    3%
      Number used as logic:                       166
      Number used as a route-thru:                 15
   Number of bonded IOBs:            25 out of    140   17%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  2,779
Additional JTAG gate count for IOBs:  1,248
Peak Memory Usage:  143 MB
Total REAL time to MAP completion:  7 secs 
Total CPU time to MAP completion:   5 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network CLKOUT2_IBUF has no load.
WARNING:MapLib:701 - Signal LED_OUT[7] connected to top level port LED_OUT(7)
   has been removed.
WARNING:MapLib:701 - Signal LED_OUT[6] connected to top level port LED_OUT(6)
   has been removed.
WARNING:MapLib:701 - Signal LED_OUT[5] connected to top level port LED_OUT(5)
   has been removed.
WARNING:MapLib:701 - Signal LED_OUT[4] connected to top level port LED_OUT(4)
   has been removed.
WARNING:MapLib:701 - Signal LED_OUT[3] connected to top level port LED_OUT(3)
   has been removed.
WARNING:MapLib:701 - Signal LED_OUT[2] connected to top level port LED_OUT(2)
   has been removed.
WARNING:MapLib:701 - Signal LED_OUT[1] connected to top level port LED_OUT(1)
   has been removed.
WARNING:MapLib:701 - Signal LED_OUT[0] connected to top level port LED_OUT(0)
   has been removed.
WARNING:MapLib:701 - Signal EXT_INT[3] connected to top level port EXT_INT(3)
   has been removed.
WARNING:MapLib:701 - Signal EXT_INT[2] connected to top level port EXT_INT(2)
   has been removed.
WARNING:MapLib:701 - Signal EXT_INT[1] connected to top level port EXT_INT(1)
   has been removed.
WARNING:MapLib:701 - Signal EXT_INT[0] connected to top level port EXT_INT(0)
   has been removed.
WARNING:LIT:113 - Dedicated Clock IO IBUFG symbol "CLKOUT2_IBUF" (output
   signal=CLKOUT2_IBUF) is not driving a global clock buffer of a DLL. This
   configuration will result in high clock skew and long net delay.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_MEMORY_15_2_4_0_a2 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net MEMORY_15_3 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_12_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_13_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_21_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_14_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_22_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_15_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_23_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_16_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_24_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_17_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_25_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_18_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net un1_TEA_26_0_a2 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.