代码搜索：combinatorial
找到约 224 项符合「combinatorial」的源代码
代码结果 224
www.eeworm.com/read/368285/9702743
v generic_fifo_sc_b.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Universal FIFO Single Clock
www.eeworm.com/read/376227/9324242
sum xupsd.sum
***********************************************************************
PSDsoft Express Version 7.80
Summary of Design Assistant
******************
www.eeworm.com/read/464438/7158465
bgn top_fpga_demo.bgn
Release 7.1.01i - Bitgen H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
"top_
www.eeworm.com/read/155172/11891879
sum fapiao.sum
***********************************************************************
PSDsoft Express Version 8.50
Summary of Design Assistant
******************
www.eeworm.com/read/127695/14340063
ini amir_1.ini
[ProjectInfo]
Project=amir_1
Directory=E:\PSDexpress\my_project
Device Family=uPSD3000
PartName=uPSD3234A
Template=
Package=U (80-Pin TQFP)
MCUManufacturer=STMicroelectronics
MCUType=uPSD32XX
www.eeworm.com/read/221576/14737133
pld mux.pld
Name MUX;
Partno ;
Revision 01;
Date 8/11/95;
Designer PLD Expert;
Company Atmel Corp.;
Location None;
Assembly None;
Device
www.eeworm.com/read/221024/14768013
html http:^^www.cs.ucdavis.edu^faculty^gusfield.html
Server: Netscape-Communications/1.1
Date: Thursday, 21-Nov-96 20:18:45 GMT
Last-modified: Friday, 23-Aug-96 20:34:02 GMT
Content-length: 911
Content-type: text/html
Daniel M. Gusf
www.eeworm.com/read/374512/9401395
drc clock.drc
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXN_56 is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-fl
www.eeworm.com/read/176855/9482341
drc cpu.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net u3_u1__n0002 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into