📄 cpu.drc

📁 用VHDL 编写的一个16位的cpu 设计方案

💻 DRC

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WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net u3_u1__n0002 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net u3__n0096 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.DRC detected 0 errors and 2 warnings.

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