代码搜索:bench
找到约 3,833 项符合「bench」的源代码
代码结果 3,833
www.eeworm.com/read/345878/3196052
s dhry_2.s
.file "c:/at91/software/projects/bench/source/dhry_2.c"
.option svr4
.option arm_code
.option inter
.ident "hc4.5a -O7 \n"
.option noswst
.seg ".text",text
.option code32,inter
.L00TEX
www.eeworm.com/read/345878/3196054
s com_baud.s
.file "c:/at91/software/projects/bench/source/com_baud.c"
.option svr4
.option arm_code
.option inter
.ident "hc4.5a -O7 \n"
.option noswst
.seg ".text",text
.option code32,inter
.L00T
www.eeworm.com/read/345878/3196055
s lib_at91.s
.file "c:/at91/software/projects/bench/source/lib_at91.c"
.option svr4
.option arm_code
.option inter
.ident "hc4.5a -O7 \n"
.option noswst
.seg ".rodata1",rodata
.L00STRING2:
.align 4
www.eeworm.com/read/345878/3196064
s dhry_2.s
.file "c:/at91/software/projects/bench/source/dhry_2.c"
.option svr4
.option thumb_code
.option inter
.ident "hc4.5a -O7 \n"
.option noswst
.seg ".text",text
.option code16,inter
.L00T
www.eeworm.com/read/297137/3889739
entries
/Makefile/1.12/Tue Aug 14 14:31:47 2001//
/bench.volmap/1.11/Wed May 30 16:04:29 2001//
/ckbench.c/1.13/Thu May 24 04:38:06 2001//
/test.imgmap.i486/1.10/Sat May 26 18:15:41 2001//
D
www.eeworm.com/read/198746/6786452
ant mvbc3tbw.ant
// D:\2006\FPGA_DESIGN\MVBC3\MVBC3
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Wed Jan 10 21:08:37 2007
`timescale 1ns/1ns
module mvbc3tbw;
reg clk;
reg rst;
reg
www.eeworm.com/read/203062/15366278
old xoopic_timings.old
/bin/time xoopic -i bench1.inp -s 200 -nox
Platform, compiler time expected time (from SPEC)
Microway500, g++2.7.2 209.6 235 (note E for flags, config)
DEC2100/5/250, g++2.7.2 423 384
DEC200/4
www.eeworm.com/read/446564/7576683
mti run.mti
#! /bin/env bash
vlog ../bench/ahb2wb_tb.v
vsim -novopt -c work.ahb2wb_tb -do "log -r /*; run -all; quit -f" 2>&1 | tee transcript.log
echo "Converting to vcd ..."
wlf2vcd vsim.wlf > vsim.vcd
gtkwave
www.eeworm.com/read/314805/13558746
ant wave-v.ant
-- E:\资料\计算机设计与实践\MYCPU16
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Nov 11 23:32:44 2007
LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LI
www.eeworm.com/read/314805/13558921
ant alu-wave.ant
-- E:\资料\计算机设计与实践\MYCPU16
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Nov 11 22:53:07 2007
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IE