alu-wave.ant

16位cpu设计VHDL源码

-- E:\资料\计算机设计与实践\MYCPU16
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Nov 11 22:53:07 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY alu-wave IS
END alu-wave;

ARCHITECTURE testbench_arch OF alu-wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\资料\计算机设计与实践\mycpu16\alu-wave.ano";
	COMPONENT alu
		PORT (
			T2 : In  std_logic;
			T3 : In  std_logic;
			clk : In  std_logic;
			Rupdate : In  std_logic;
			Radd : In  std_logic_vector (2 DOWNTO 0);
			Rdata : In  std_logic_vector (7 DOWNTO 0);
			IRout : In  std_logic_vector (15 DOWNTO 0);
			MRD_C : Out  std_logic;
			MWR_C : Out  std_logic;
			Addr : Out  std_logic_vector (15 DOWNTO 0);
			ALUout : Out  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL T2 : std_logic;
	SIGNAL T3 : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL Rupdate : std_logic;
	SIGNAL Radd : std_logic_vector (2 DOWNTO 0);
	SIGNAL Rdata : std_logic_vector (7 DOWNTO 0);
	SIGNAL IRout : std_logic_vector (15 DOWNTO 0);
	SIGNAL MRD_C : std_logic;
	SIGNAL MWR_C : std_logic;
	SIGNAL Addr : std_logic_vector (15 DOWNTO 0);
	SIGNAL ALUout : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : alu
	PORT MAP (
		T2 => T2,
		T3 => T3,
		clk => clk,
		Rupdate => Rupdate,
		Radd => Radd,
		Rdata => Rdata,
		IRout => IRout,
		MRD_C => MRD_C,
		MWR_C => MWR_C,
		Addr => Addr,
		ALUout => ALUout
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_MRD_C(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",MRD_C,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, MRD_C);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_MWR_C(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",MWR_C,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, MWR_C);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_Addr(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Addr,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Addr);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_ALUout(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",ALUout,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ALUout);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_MRD_C(TX_TIME);
		ANNOTATE_MWR_C(TX_TIME);
		ANNOTATE_Addr(TX_TIME);
		ANNOTATE_ALUout(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		T2 <= transport '0';
		T3 <= transport '0';
		Rupdate <= transport '0';
		Radd <= transport std_logic_vector'("000"); --0
		Rdata <= transport std_logic_vector'("00000000"); --0
		IRout <= transport std_logic_vector'("0000000000000000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION alu_cfg OF alu-wave IS
	FOR testbench_arch
	END FOR;
END alu_cfg;