代码搜索：asynchronous
找到约 2,366 项符合「asynchronous」的源代码
代码结果 2,366
www.eeworm.com/read/489686/6468811
v reginf.v
// MAX+plus II Verilog Example
// Register Inference
// Copyright (c) 1997 Altera Corporation
module reginf(d, clk, clr, pre, load, data,
q1, q2, q3, q4, q5, q6, q7);
input d, clk, clr,
www.eeworm.com/read/401301/11559730
v reginf.v
// MAX+plus II Verilog Example
// Register Inference
// Copyright (c) 1997 Altera Corporation
module reginf(d, clk, clr, pre, load, data,
q1, q2, q3, q4, q5, q6, q7);
input d, clk, clr,
www.eeworm.com/read/157781/11663146
v ddr_input.v
//
// Module: DDR_Input
//
// Description: Verilog instantiation template
// Double Data Rate Input
//
//
// Device: VIRTEX-II Family
//--------------------------------------------------
www.eeworm.com/read/259003/11827824
v row_signal.v
module Row_Signal (Row, Key, Col);
output [3:0] Row;
input [15:0] Key;
input [3:0] Col;
reg Row;
// Scan for row of the asserted key
always @ (Key or Col) begin //As
www.eeworm.com/read/258642/11848868
v row_signal.v
module Row_Signal (Row, Key, Col);
output [3:0] Row;
input [15:0] Key;
input [3:0] Col;
reg [3:0] Row;
// Scan for row of the asserted key
always @ (Key or Col) begin
www.eeworm.com/read/254980/12110212
v reginf.v
// MAX+plus II Verilog Example
// Register Inference
// Copyright (c) 1997 Altera Corporation
module reginf(d, clk, clr, pre, load, data,
q1, q2, q3, q4, q5, q6, q7);
input d, clk, clr,
www.eeworm.com/read/131833/14123045
vb userconnection.vb
Option Strict On
Imports System.Net.Sockets
Imports System.Text
' The UserConnection class encapsulates the functionality of a TcpClient connection
' with streaming for a single user.
Public
www.eeworm.com/read/233704/14142815
bak dff.bak
module dff_asynchronous(q,d,clear,clk);
output q;
input d,clear,clk;
reg q;
always@(clear)
if(!clear)
q=0;
always@(negedge clk)
if(!clear)
q=0;
else
q=d;
endmodule
www.eeworm.com/read/233704/14142853
v dff_asychronous.v
module dff_asynchronous(q,d,clear,clk);
output q;
input d,clear,clk;
reg q;
always@(clear)
if(!clear)
q=0;
always@(negedge clk)
if(!clear)
q=0;
else
q=d;
endmodule
www.eeworm.com/read/126327/14428477
v reginf.v
// MAX+plus II Verilog Example
// Register Inference
// Copyright (c) 1997 Altera Corporation
module reginf(d, clk, clr, pre, load, data,
q1, q2, q3, q4, q5, q6, q7);
input d, clk, clr,