ddr_input.v

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//
// Module: 	DDR_Input
//
// Description: Verilog instantiation template
//		Double Data Rate Input
//		
//
// Device: 	VIRTEX-II Family 
//--------------------------------------------------------------------------

module ddr_input (data_in, q1, q2, clk, rst);

input data_in, clk, rst;

output q1, q2;
reg q1, q2;


//Describe input DDR registers (behaviorally) to be inferred

always @ (posedge clk or posedge rst) //rising-edge DDR reg and asynchronous reset

  begin
	if (rst) 
	   q1 = 1'b0;
	else 
	   q1 = data_in;
  end 

always @ (negedge clk or posedge rst) //falling-edge DDR reg and asynchronous reset

begin
	if (rst) 
	   q2 = 1'b0;
	else 
	   q2 = data_in;
  end 

endmodule