代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/323875/3507452
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity Adder4x8 is
port(
\out\ : out vl_logic_vector(31 downto 0);
cout : out vl_logic;
\of\
www.eeworm.com/read/323875/3507455
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity Adder16_M is
port(
sum : out vl_logic_vector(15 downto 0);
cout : out vl_logic;
P
www.eeworm.com/read/323875/3507466
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity Adder4_M is
port(
sum : out vl_logic_vector(3 downto 0);
cout : out vl_logic;
P
www.eeworm.com/read/470676/1467885
vhd addern.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--USE WORK.adder_pkg.ALL;
ENTITY adderN IS
GENERIC (n : INTEGER :=7);
PORT (A : IN std_logic_vector(n DOWNTO 0);
B
www.eeworm.com/read/193974/5138283
py test_scope.py
from test_support import verify, TestFailed, check_syntax
import warnings
warnings.filterwarnings("ignore", r"import \*", SyntaxWarning, "")
print "1. simple nesting"
def make_adder(x):