addern.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--USE WORK.adder_pkg.ALL;

ENTITY adderN IS 
       GENERIC (n : INTEGER :=7);
           PORT (A   : IN  std_logic_vector(n DOWNTO 0);
	         B   : IN  std_logic_vector(n DOWNTO 0);
	         Cin : IN  std_logic;
	         Co  : OUT std_logic;
	         S   : OUT std_logic_vector(n DOWNTO 0));
END adderN;

ARCHITECTURE structure_arc OF adderN IS
         COMPONENT full_adder
            PORT (A   : IN  std_logic;
	          B   : IN  std_logic;
	          Cin : IN  std_logic;
	          Co  : OUT std_logic;
	          S   : OUT std_logic);
         END COMPONENT;
         SIGNAL  carry_tmp  : std_logic_vector(n-1 DOWNTO 0);
BEGIN
     G1: FOR i IN 0 TO n GENERATE
         P1:IF (i = 0) GENERATE
             adderx: full_adder
             PORT MAP (A(i),B(i),Cin,carry_tmp(i),S(i));
         END GENERATE P1;

         P2:IF (i = n) GENERATE
             adderx: full_adder
             PORT MAP (A(i),B(i),carry_tmp(i-1),Co,S(i));
         END GENERATE P2;

         P3:IF ((i /= 0) AND (i /= n)) GENERATE
             adderx: full_adder
             PORT MAP (A(i),B(i),carry_tmp (i-1),carry_tmp (i),S(i));
         END GENERATE P3;
     END GENERATE G1;
END structure_arc;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY full_adder IS 
        PORT (A,B : IN  std_logic;
              Cin : IN  std_logic;
              Co  : OUT std_logic;
              S   : OUT std_logic);
END full_adder; 

ARCHITECTURE rtl OF full_adder IS
         SIGNAL  tmp1,tmp2  : std_logic; 
BEGIN
	     tmp1 <= A XOR B;
	     tmp2 <= tmp1 AND Cin;
	     S <= tmp1 XOR Cin;
	     Co <= tmp2 OR (A AND B);
END rtl;