代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/246188/12752035
4++
4位乘法器,vhdl--我们的技术是您的(o4icwin & wyouken)！ www.icwin.netAD
[经验代码]->[FPGA 开发经验]->4位乘法器,vhdl
4位乘法器,vhdl
4位乘法器,vhdl
www.eeworm.com/read/139799/13130648
vhd example11-21.vhd
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY full_adder IS
GENERIC (delay_sum, delay_carry : TIME);
PORT (in1, in2, carry_in : IN Std_Logic;
sum, carry_out : OUT Std_Logic);
END
www.eeworm.com/read/319928/13439371
xrf alu_modelsim.xrf
vendor_name = ModelSim
source_file = 1, F:/Quartus5.0/cyzhangFile/ALU/reg.vhd
source_file = 1, F:/Quartus5.0/cyzhangFile/ALU/ALU.vhd
source_file = 1, F:/Quartus5.0/cyzhangFile/adder16/add4.vhd
sou
www.eeworm.com/read/310713/13645243
vo dds.vo
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
www.eeworm.com/read/492910/6413851
txt 全加器仿真程序.txt
全加器仿真程序。
LIBRARY IEEE;
USE STD_TEXTIO.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
ENTITY test_fadder IS
END ENTITY test_fadder;
ARCHITECTURE arc1 OF test_fadde
www.eeworm.com/read/479485/6687367
vhd ddsc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
library lpm;
use lpm.lpm_components.all;
entity ddsc is
generic( freq_width : intege
www.eeworm.com/read/479485/6687379
bak ddsc.vhd.bak
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
library lpm;
use lpm.lpm_components.all;
entity ddsc is
generic( freq_width : intege
www.eeworm.com/read/478303/6714511
vhd ex_p4_28_bcd_add.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BCD_ADDER is
port (A,B:in std_logic_VECTOR(3 downto 0);
S: out std_logic_VECTOR(3 downto 0);
Cin : in
www.eeworm.com/read/478253/6722867
vhd dds32_1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
library lpm; -- Altera LPM
use lpm.lpm_components.all;
entity dds32_1 is
www.eeworm.com/read/402598/11532291
rpt signal_gene.sim.rpt
Simulator report for signal_gene
Tue Dec 30 01:48:45 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
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1. Le