dds.vo

直接数字频率合成器

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.2 Build 157 12/07/2004 SJ Full Version"

// DATE "05/08/2006 10:24:01"

// 
// Device: Altera EPF10K10LC84-3 Package PLCC84
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	dds (
	clk,
	phase,
	freword,
	sinvalue);
input 	clk;
input 	[8:0] phase;
input 	[8:0] freword;
output 	[9:0] sinvalue;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("dds_v.sdo");
// synopsys translate_on

wire \inst|lpm_ff_component|dffs[0] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[0] ;
wire \phase[1]~dataout ;
wire \phase[2]~dataout ;
wire \phase[3]~dataout ;
wire \phase[4]~dataout ;
wire \phase[5]~dataout ;
wire \phase[6]~dataout ;
wire \phase[7]~dataout ;
wire \freword[1]~dataout ;
wire \freword[2]~dataout ;
wire \freword[3]~dataout ;
wire \freword[4]~dataout ;
wire \freword[5]~dataout ;
wire \freword[6]~dataout ;
wire \freword[7]~dataout ;
wire \clk~dataout ;
wire \phase[0]~dataout ;
wire \inst4|lpm_add_sub_component|adder|result_node|cs_buffer[0] ;
wire \freword[0]~dataout ;
wire \inst6|lpm_add_sub_component|adder|result_node|cout[0] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[1] ;
wire \inst|lpm_ff_component|dffs[1] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cout[0] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cs_buffer[1] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cout[1] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[2] ;
wire \inst|lpm_ff_component|dffs[2] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cout[1] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cs_buffer[2] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cout[2] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[3] ;
wire \inst|lpm_ff_component|dffs[3] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cout[2] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cs_buffer[3] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cout[3] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[4] ;
wire \inst|lpm_ff_component|dffs[4] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cout[3] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cs_buffer[4] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cout[4] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[5] ;
wire \inst|lpm_ff_component|dffs[5] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cout[4] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cs_buffer[5] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cout[5] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[6] ;
wire \inst|lpm_ff_component|dffs[6] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cout[5] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cs_buffer[6] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cout[6] ;
wire \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[7] ;
wire \inst|lpm_ff_component|dffs[7] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cout[6] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cs_buffer[7] ;
wire \phase[8]~dataout ;
wire \freword[8]~dataout ;
wire \inst6|lpm_add_sub_component|adder|result_node|cout[7] ;
wire \inst6|lpm_add_sub_component|adder|unreg_res_node[8] ;
wire \inst|lpm_ff_component|dffs[8] ;
wire \inst4|lpm_add_sub_component|adder|result_node|cout[7] ;
wire \inst4|lpm_add_sub_component|adder|unreg_res_node[8] ;
wire \inst3|lpm_rom_component|srom|q[9] ;
wire \inst3|lpm_rom_component|srom|q[8] ;
wire \inst3|lpm_rom_component|srom|q[7] ;
wire \inst3|lpm_rom_component|srom|q[6] ;
wire \inst3|lpm_rom_component|srom|q[5] ;
wire \inst3|lpm_rom_component|srom|q[4] ;
wire \inst3|lpm_rom_component|srom|q[3] ;
wire \inst3|lpm_rom_component|srom|q[2] ;
wire \inst3|lpm_rom_component|srom|q[1] ;
wire \inst3|lpm_rom_component|srom|q[0] ;


// atom is at LC3_B10
flex10ke_lcell \inst|lpm_ff_component|dffs[0]~I (
// Equation(s):
// \inst|lpm_ff_component|dffs[0]  = DFFEA(\inst6|lpm_add_sub_component|adder|result_node|cs_buffer[0] , GLOBAL(\clk~dataout ), , , , , )

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\inst6|lpm_add_sub_component|adder|result_node|cs_buffer[0] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst|lpm_ff_component|dffs[0] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst|lpm_ff_component|dffs[0]~I .operation_mode = "normal";
defparam \inst|lpm_ff_component|dffs[0]~I .packed_mode = "false";
defparam \inst|lpm_ff_component|dffs[0]~I .lut_mask = "FF00";
defparam \inst|lpm_ff_component|dffs[0]~I .clock_enable_mode = "false";
defparam \inst|lpm_ff_component|dffs[0]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at PIN_44
flex10ke_io \phase[1]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\phase[1]~dataout ),
	.padio(phase[1]));
// synopsys translate_off
defparam \phase[1]~I .operation_mode = "input";
defparam \phase[1]~I .reg_source_mode = "none";
defparam \phase[1]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at PIN_42
flex10ke_io \phase[2]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\phase[2]~dataout ),
	.padio(phase[2]));
// synopsys translate_off
defparam \phase[2]~I .operation_mode = "input";
defparam \phase[2]~I .reg_source_mode = "none";
defparam \phase[2]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at PIN_1
flex10ke_io \phase[3]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\phase[3]~dataout ),
	.padio(phase[3]));
// synopsys translate_off
defparam \phase[3]~I .operation_mode = "input";
defparam \phase[3]~I .reg_source_mode = "none";
defparam \phase[3]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at PIN_6
flex10ke_io \phase[4]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\phase[4]~dataout ),
	.padio(phase[4]));
// synopsys translate_off
defparam \phase[4]~I .operation_mode = "input";
defparam \phase[4]~I .reg_source_mode = "none";
defparam \phase[4]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at PIN_3
flex10ke_io \phase[5]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\phase[5]~dataout ),
	.padio(phase[5]));
// synopsys translate_off
defparam \phase[5]~I .operation_mode = "input";
defparam \phase[5]~I .reg_source_mode = "none";
defparam \phase[5]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at PIN_67
flex10ke_io \phase[6]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\phase[6]~dataout ),
	.padio(phase[6]));
// synopsys translate_off
defparam \phase[6]~I .operation_mode = "input";
defparam \phase[6]~I .reg_source_mode = "none";
defparam \phase[6]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at PIN_9
flex10ke_io \phase[7]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\phase[7]~dataout ),
	.padio(phase[7]));
// synopsys translate_off
defparam \phase[7]~I .operation_mode = "input";
defparam \phase[7]~I .reg_source_mode = "none";
defparam \phase[7]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at LC5_B9
flex10ke_lcell \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[0]~I (
// Equation(s):
// \inst6|lpm_add_sub_component|adder|result_node|cs_buffer[0]  = \inst|lpm_ff_component|dffs[0]  $ \freword[0]~dataout 
// \inst6|lpm_add_sub_component|adder|result_node|cout[0]  = CARRY(\inst|lpm_ff_component|dffs[0]  & \freword[0]~dataout )

	.dataa(\inst|lpm_ff_component|dffs[0] ),