代码搜索:adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/478253/6722866
vhd dds_dds.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY dds_dds IS
port(ftw: in std_logic_vector(23 downto 0); --频率控制字
clk: in
www.eeworm.com/read/263510/11359994
vhd dds_dds.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY dds_dds IS
port(ftw: in std_logic_vector(23 downto 0); --频率控制字
clk: in
www.eeworm.com/read/402018/11544048
vhd dds_dds.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY dds_dds IS
port(ftw: in std_logic_vector(23 downto 0); --频率控制字
clk: in
www.eeworm.com/read/401684/11551882
rpt div.fit.rpt
Fitter report for div
Tue Nov 25 10:38:05 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
www.eeworm.com/read/261127/11665696
rpt sec.rpt
Project Information e:\kai\timer\sec.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 05/16/2007 20:56:42
Copyright (C) 1988-1999 Alter
www.eeworm.com/read/260654/11712782
hif alu.hif
HIF003
--
-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
www.eeworm.com/read/260654/11713107
hif lzcpu.hif
HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
www.eeworm.com/read/344530/11874260
eqn frequency.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/155382/11881530
v signal.v
/*-----------------------------------------------*-
File for signal sourse
-*-----------------------------------------------*/
module signal(reset,clk,step_value,phase_addr1,phase_addr2);
input
www.eeworm.com/read/151962/12156972
rpt ecc_new2.rpt
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\ecc_new2.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 06/10/2004 16:51: