ecc_new2.rpt

用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能

Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\ecc_new2.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 06/10/2004 16:51:37

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

ecc_new2  EPF10K10LC84-3   4      19     0    0         0  %    402      69 %

User Pins:                 4      19     0  



Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\ecc_new2.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Flipflop '|route_new1:90|:120' stuck at GND
Warning: Flipflop '|fdiv_cnt_new:83|fdiv12:70|:102' stuck at GND
Warning: Flipflop '|fdiv_cnt_new:83|fdiv12:70|:101' stuck at GND
Warning: Flipflop '|fdiv_cnt_new:83|fdiv28_31:57|:499' stuck at GND
Warning: Flipflop '|fdiv_cnt_new:83|fdiv12:70|:100' stuck at GND
Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.


Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\ecc_new2.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

ecc_new2@53                       alarm
ecc_new2@1                        clk
ecc_new2@24                       dp
ecc_new2@44                       mode
ecc_new2@23                       out0
ecc_new2@22                       out1
ecc_new2@21                       out2
ecc_new2@19                       out3
ecc_new2@18                       out4
ecc_new2@17                       out5
ecc_new2@16                       out6
ecc_new2@78                       scan_en1
ecc_new2@79                       scan_en2
ecc_new2@80                       scan_en3
ecc_new2@81                       scan_en4
ecc_new2@10                       scan_en5
ecc_new2@11                       scan_en6
ecc_new2@84                       select
ecc_new2@83                       set


Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme4\ecc_new2.rpt

** FILE HIERARCHY **



|p7segment:12|
|clkdiv250:49|
|clkdiv250:49|lpm_add_sub:80|
|clkdiv250:49|lpm_add_sub:80|addcore:adder|
|clkdiv250:49|lpm_add_sub:80|altshift:result_ext_latency_ffs|
|clkdiv250:49|lpm_add_sub:80|altshift:carry_ext_latency_ffs|
|clkdiv250:49|lpm_add_sub:80|altshift:oflow_ext_latency_ffs|
|clkdiv10:53|
|clkdiv10:53|lpm_add_sub:32|
|clkdiv10:53|lpm_add_sub:32|addcore:adder|
|clkdiv10:53|lpm_add_sub:32|altshift:result_ext_latency_ffs|
|clkdiv10:53|lpm_add_sub:32|altshift:carry_ext_latency_ffs|
|clkdiv10:53|lpm_add_sub:32|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|
|fdiv_cnt_new:83|fdiv100:52|
|fdiv_cnt_new:83|fdiv100:52|lpm_add_sub:51|
|fdiv_cnt_new:83|fdiv100:52|lpm_add_sub:51|addcore:adder|
|fdiv_cnt_new:83|fdiv100:52|lpm_add_sub:51|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv100:52|lpm_add_sub:51|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv100:52|lpm_add_sub:51|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:53|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:96|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:96|addcore:adder|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:96|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:96|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:96|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:97|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:97|addcore:adder|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:97|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:97|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:53|lpm_add_sub:97|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:54|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:96|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:96|addcore:adder|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:96|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:96|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:96|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:97|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:97|addcore:adder|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:97|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:97|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv60:54|lpm_add_sub:97|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv24:55|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:96|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:96|addcore:adder|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:96|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:96|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:96|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:97|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:97|addcore:adder|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:97|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:97|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv24:55|lpm_add_sub:97|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:554|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:554|addcore:adder|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:554|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:554|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:554|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:555|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:555|addcore:adder|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:555|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:555|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:555|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:556|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:556|addcore:adder|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:556|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:556|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:556|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:557|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:557|addcore:adder|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:557|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:557|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:557|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:558|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:558|addcore:adder|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:558|altshift:result_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:558|altshift:carry_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:558|altshift:oflow_ext_latency_ffs|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:559|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:559|addcore:adder|
|fdiv_cnt_new:83|fdiv28_31:57|lpm_add_sub:559|altshift:result_ext_latency_ffs|