代码搜索：adder

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/489559/1217060

h adder.h

/* * Copyright (C) 2004-2005 Arabella Software Ltd. * Yuli Barcohen * * Support for Analogue&Micro Adder boards family. * Tested on AdderII and Adder87x. * * See file CRED
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www.eeworm.com/read/489559/1219069

c adder.c

/* * Copyright (C) 2004-2005 Arabella Software Ltd. * Yuli Barcohen * * Support for Analogue&Micro Adder boards family. * Tested on AdderII and Adder87x. * * See file CRED
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www.eeworm.com/read/483857/1274562

xco adder.xco

############################################################## # # Xilinx Core Generator version i+IP+122117 # Date: Sun Sep 09 14:00:29 2007 # ########################################################
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www.eeworm.com/read/478903/1348174

xst adder.xst

set -tmpdir __projnav set -xsthdpdir ./xst run -ifn adder.prj -ifmt mixed -ofn adder -ofmt NGC -p xc2s200-6-pq208 -top adder -opt_mode Speed -opt_level 1 -iuc NO -lso adder.lso -keep_hier
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www.eeworm.com/read/478903/1348180

gfl adder.gfl

# XST (Creating Lso File) : adder.lso # xst flow : RunXST adder.syr adder.prj adder.sprj adder.ana adder.stx adder.cmd_log adder.ngc adder.ngr # Implmentation : Translate __projnav/ngdbui
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www.eeworm.com/read/474522/1393497

h adder.h

//////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / // \ \ \/ // \ \ Copyright (c) 2003-2004 X
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www.eeworm.com/read/472524/1409957

java adder.java

public class Adder { public static void main(String[] args) { int numArgs = args.length; //this program requires at least two arguments on the command line if (numArgs < 2) {
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www.eeworm.com/read/471038/1435067

java adder.java

public class Adder { public static void main(String[] args) { int numArgs = args.length; //this program requires at least two arguments on the command line if (numArgs < 2) {
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www.eeworm.com/read/470676/1467795

vhd adder.vhd

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY adder IS PORT (a : IN std_logic_vector(7 DOWNTO 0); b : IN std_logic_vector(7 DOWNT
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www.eeworm.com/read/470676/1467865

vhd adder.vhd

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY adder IS PORT (a : IN std_logic_vector(7 DOWNTO 0); b : IN std_logic_vector(7 DOWNTO
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