adder.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY adder IS
           PORT (a   : IN  std_logic_vector(7 DOWNTO 0);
	         b   : IN  std_logic_vector(7 DOWNTO 0);
	         cs  : IN  std_logic;
	         q   : OUT std_logic_vector(7 DOWNTO 0));
END adder; 
 
ARCHITECTURE behave OF adder IS
BEGIN
         PROCESS(cs)
         BEGIN
	      IF (cs ='1') THEN
		  q <= a+b;
              END IF;
         END PROCESS;
END behave;