adder.gfl

一个verilog的源码程序

# XST (Creating Lso File) : 
adder.lso
# xst flow : RunXST
adder.syr
adder.prj
adder.sprj
adder.ana
adder.stx
adder.cmd_log
adder.ngc
adder.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\adder\ise\adder/_ngo
adder.ngd
adder_ngdbuild.nav
adder.bld
.untf
adder.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\adder\ise\adder/_ngo
adder.ngd
adder_ngdbuild.nav
adder.bld
adder.ucf.untf
adder.cmd_log
# Implementation : Map
adder_map.ncd
adder.ngm
adder.pcf
adder.nc1
adder.mrp
adder_map.mrp
adder.mdf
__projnav/map.log
adder.cmd_log
MAP_NO_GUIDE_FILE_CPF "adder"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
adder.twr
adder.twx
adder.tsi
adder.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
adder.ncd
adder.par
adder.pad
adder_pad.txt
adder_pad.csv
adder.pad_txt
adder.dly
reportgen.log
adder.xpi
adder.grf
adder.itr
adder_last_par.ncd
__projnav/par.log
adder.placed_ncd_tracker
adder.routed_ncd_tracker
adder.cmd_log
PAR_NO_GUIDE_FILE_CPF "adder"
# Generate Programming File
__projnav/adder_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
adder.ut
# Programming File Generation Report
adder.bgn
adder.rbt
adder.ll
adder.msk
adder.drc
adder.nky
adder.bit
adder.bin
adder.isc
adder.cmd_log