代码搜索:adder

找到约 6,792 项符合「adder」的源代码

代码结果 6,792
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v adder.v

// megafunction wizard: %LPM_ADD_SUB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: lpm_add_sub // ============================================================ // File Name: adder.v //
www.eeworm.com/read/214503/15098217

dhp adder.dhp

www.eeworm.com/read/214503/15098248

gfl adder.gfl

# XST (Creating Lso File) : adder4.lso # xst flow : RunXST adder4.syr adder4.prj adder4.sprj adder4.ana adder4.stx adder4.cmd_log adder4.ngr # View RTL Schematic adder4.ngr # Verilog : Cr
www.eeworm.com/read/214503/15098268

npl adder.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT adder DESIGN adder DEVFAM spartan2 DEVFAMTIME 1134882729 DEVICE xc2s15 DEVICETIME 1134882729 DEVPKG cs144 DEVPKGTIME 1134882729 DEVSPEED
www.eeworm.com/read/213968/15119158

v adder.v

module adder(xin1,xin2,xout); //加法器模块 input[7:0] xin1,xin2; //定义输入的x(i)和x(N-i-1) output[8:0] xout; //定义加和输出 wire cout1,cout2,cout3,cout4,cout5; //中间变量定义 wire [3:0] out1,out2; wire out3,
www.eeworm.com/read/205700/15309651

vhd adder.vhd

library ieee; use ieee.std_logic_1164.all; entity adder is port( a,b,cin :in std_logic; s,cout :out std_logic ); end adder; architecture aa of adder is signal p,g:std_logic; begin
www.eeworm.com/read/8141/142073

ewb adder.ewb

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "This circuit adds two 3-bit numbers. It uses 3 full-adders in parallel to add the individual bits in order to obtain the
www.eeworm.com/read/9238/165644

pcbdoc adder.pcbdoc

www.eeworm.com/read/9238/165646

prjpcb adder.prjpcb

[Design] Version=1.0 HierarchyMode=0 ChannelRoomNamingStyle=0 OutputPath= ChannelDesignatorFormatString=$Component_$RoomName ChannelRoomLevelSeperator=_ OpenOutputs=1 ArchiveProject=0 Timesta
www.eeworm.com/read/14063/292981

ewb adder.ewb

Electronics Workbench Circuit File Version: 5 Charset: ANSI Description: "This circuit adds two 3-bit numbers. It uses 3 full-adders in parallel to add the individual bits in order to obtain the