adder.v

Verilog 编写的fir滤波器

module adder(xin1,xin2,xout);  //加法器模块
input[7:0] xin1,xin2;  //定义输入的x(i)和x(N-i-1)
output[8:0] xout;     //定义加和输出
wire cout1,cout2,cout3,cout4,cout5;     //中间变量定义
wire [3:0] out1,out2;
wire out3,out4; 
wire sel;
wire m1;
fouradder fouraddera(xin1[3:0],xin2[3:0],1'b0,xout[3:0],cout1);      //低四位通过超前进位加法器得出
fouradder fouradderb(xin1[7:4],xin2[7:4],1'b0,out1,cout2);         //中间四位通过进位选择加法器得出
fouradder fouradderc(xin1[7:4],xin2[7:4],1'b1,out2,cout3);
fa fa1(xin1[7],xin2[7],1'b0,out3,cout4);                   //最高位通过进位选择加法器得出
fa fa2(xin1[7],xin2[7],1'b1,out4,cout5);
twomux twomux1(out1,out2,cout1,xout[7:4]);           //选择出中间四位
or(m1,cout1,cout2);
and(sel,m1,cout3);
twomuxs twomuxs1(out3,out4,sel,xout[8]);         //选择最高位
endmodule