adder.gfl

这是个基于 Xilinx Spartan3 的加法器

# XST (Creating Lso File) : 
adder4.lso
# xst flow : RunXST
adder4.syr
adder4.prj
adder4.sprj
adder4.ana
adder4.stx
adder4.cmd_log
adder4.ngr
# View RTL Schematic
adder4.ngr
# Verilog : Create Schematic Symbol
adder4.spl
__projnav/jhdparse.log
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Launch ModelSim Simulator
adder4.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
adder4_adder4t_v_tf.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
adder4_adder4t_v_tf.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
adder4_adder4t_v_tf.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# View RTL Schematic
adder4.ngr
# xst flow : RunXST
adder4.syr
adder4.prj
adder4.sprj
adder4.ana
adder4.stx
adder4.cmd_log
adder4.ngc
adder4.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\xilinxlab\myfirst\adder/_ngo
adder4.ngd
adder4_ngdbuild.nav
adder4.bld
.untf
adder4.cmd_log
# Implementation : Map
adder4_map.ncd
adder4.ngm
adder4.pcf
adder4.nc1
adder4.mrp
adder4_map.mrp
adder4.mdf
__projnav/map.log
adder4.cmd_log
MAP_NO_GUIDE_FILE_CPF "adder4"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
adder4.twr
adder4.twx
adder4.tsi
adder4.cmd_log
# Implmentation : Place & Route Report
__projnav/nc1TOncd_tcl.rsp
adder4.ncd
adder4.par
adder4.pad
adder4_pad.txt
adder4_pad.csv
adder4.pad_txt
adder4.dly
reportgen.log
adder4.xpi
adder4.grf
adder4.itr
adder4_last_par.ncd
__projnav/par.log
adder4.placed_ncd_tracker
adder4.routed_ncd_tracker
adder4.cmd_log
PAR_NO_GUIDE_FILE_CPF "adder4"
# View RTL Schematic
adder4.ngr
# Implementation : View/Edit Routed Design (FPGA Editor)
adder4_map_fpga_editor.log
adder4_fpga_editor.out
adder4_fpga_editor.log
__projnav/pfea_tcl.rsp
# Implmentation : View/Edit Placed Design (Floorplanner)
__projnav/parFloorPlanner.rsp
adder4.mfp
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# View RTL Schematic
adder4.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
f:\xilinxlab\myfirst\adder/_ngo
adder4.ngd
adder4_ngdbuild.nav
adder4.bld
adder4.ucf.untf
adder4.cmd_log
# Implmentation : Floorplan Design
__projnav/xlateFloorPlanner.rsp
# Implementation : Generate Post-Translate Simulation Model
adder4_translate.v
adder4_translate.v
adder4_translate.nlf
adder4.xlate_nlf
adder4.xlate_nlf
adder4.cmd_log
# Implementation : Map
adder4_map.ncd
adder4.ngm
adder4.pcf
adder4.nc1
adder4.mrp
adder4_map.mrp
adder4.mdf
__projnav/map.log
adder4.cmd_log
MAP_NO_GUIDE_FILE_CPF "adder4"
# Implementation : Manually Place & Route (FPGA Editor)
adder4_map_fpga_editor.log
adder4_fpga_editor.out
adder4_fpga_editor.log
__projnav/mfea_tcl.rsp
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
adder4.twr
adder4.twx
adder4.tsi
adder4.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
adder4.ncd
adder4.par
adder4.pad
adder4_pad.txt
adder4_pad.csv
adder4.pad_txt
adder4.dly
reportgen.log
adder4.xpi
adder4.grf
adder4.itr
adder4_last_par.ncd
__projnav/par.log
adder4.placed_ncd_tracker
adder4.routed_ncd_tracker
adder4.cmd_log
PAR_NO_GUIDE_FILE_CPF "adder4"
# Implementation : Analyze Power (XPower)
adder4.cxt
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# View RTL Schematic
adder4.ngr
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
adder4_adder4t_v_tf.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf