adder.npl

来自「这是个基于 Xilinx Spartan3 的加法器」· NPL 代码 · 共 28 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT adder
DESIGN adder
DEVFAM spartan2
DEVFAMTIME 1134882729
DEVICE xc2s15
DEVICETIME 1134882729
DEVPKG cs144
DEVPKGTIME 1134882729
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE adder4.v
STIMULUS adder4t.v
DEPASSOC adder4 adder4.ucf
[STATUS-ALL]
adder4.ncdFile=WARNINGS,1134899974
[STRATEGY-LIST]
Normal=True