代码搜索：Virtex-II

找到约 176 项符合「Virtex-II」的源代码

代码结果 176
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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txt readme_sum_of_products_verilog.txt

README file: Virtex-II Platform FPGA Handbook ============================================= Date: March, 2001 Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
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txt readme_multiplexers_verilog.txt

README file: Virtex-II Platform FPGA Handbook ============================================= Date: March, 2001 Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
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txt readme_lvds_verilog.txt

README file: Virtex-II Platform FPGA Handbook ============================================= Date: March, 2001 Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
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txt readme_ddr_verilog.txt

README file: Virtex-II Platform FPGA Handbook ============================================= Date: March, 2001 Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
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www.eeworm.com/read/157786/11663002

txt readme_shift_registers_verilog.txt

README file: Virtex-II Platform FPGA Handbook ============================================= Date: March, 2001 Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
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www.eeworm.com/read/157778/11663282

txt readme_blockram_verilog.txt

README file: Virtex-II Platform FPGA Handbook ============================================= Date: March, 2001 Verilog code examples are provided to illustrate the Chapter 2 - Design Considerati
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www.eeworm.com/read/157781/11663144

v ddr_output.v

// // Module: DDR_Output // // Description: Verilog instantiation template // Double Data Rate Output // // // Device: VIRTEX-II Family //------------------------------------------------
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v mult18x18.v

/*------------------------------------------------------------------------------- -- Virtex-II Registered Block Multiplier inference using Synplify -- ------------------------------------
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v mult18x18s.v

/*----------------------------------------------------------------------------- -- Virtex-II Registered Block Multiplier inference using Synplify -- --------------------------------------
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v mult_and.v

/*----------------------------------------------------------------------------- -- Virtex-II MULT_AND cell inference using Synplify -- --------------------------------------
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