readme_blockram_verilog.txt

本人正在学习vhdl语言

README file: Virtex-II Platform FPGA Handbook
=============================================

Date: March, 2001

Verilog code examples are provided to illustrate the Chapter 2 - Design Considerations - of 
the Virtex-II Platform FPFA Handbook.

- Verilog Templates:
Verilog templates are available as examples to instantiate primitives. 

- Verilog Submodules:
Verilog submodules are low level Verilog code instantiating some primitives. 
These submodules can be instantiated in a design and must be synthesized with the design.

The templates and submodules can be found in the following directories corresponding to 
each section of the Chapter 2: Design Considerations (Virtex-II Platform FPGA HandBook)

Directory:
------------

- blockram: "Using Block SelectRAM Memory"

Templates (primitive):
 
 Single-port templates:
  SelectRAM_A1
  SelectRAM_A2
  SelectRAM_A4
  SelectRAM_A9
  SelectRAM_A18
  SelectRAM_A36

 Dual-port templates:
  SelectRAM_A1_B1
  SelectRAM_A1_B2
  SelectRAM_A1_B4
  SelectRAM_A1_B9
  SelectRAM_A1_B18
  SelectRAM_A1_B36
  SelectRAM_A2_B2
  SelectRAM_A2_B4
  SelectRAM_A2_B9
  SelectRAM_A2_B18
  SelectRAM_A2_B36
  SelectRAM_A4_B4
  SelectRAM_A4_B9
  SelectRAM_A4_B18
  SelectRAM_A4_B36
  SelectRAM_A9_B9
  SelectRAM_A9_B18
  SelectRAM_A9_B36
  SelectRAM_A18_B18
  SelectRAM_A18_B36
  SelectRAM_A36_B36

Example:
 XC2V_RAMB_1_PORT


Who to Contact if you have questions?

http://support.xilinx.com/

North American Support
Hotline: [phone] 
or [phone] 
Fax: [phone] 
Email: [e-mail] 
 
United Kingdom Support
Hotline: [phone]
Fax: [phone] 
Email : [e-mail] 
 
Japan Support
Hotline: Local Distributor
Fax: Local Distributor
Email: [e-mail]