mult18x18s.v

Xilinx Ise 官方源代码盘 第四章

/*-----------------------------------------------------------------------------
--      Virtex-II Registered Block Multiplier inference using Synplify       --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II MULT18X18 cells from behavioral 
--   multiplier descriptions.
--
-- The multiplier resources: (See Virtex-II Handbook for more details)
--     - Logic (CLB resources)
--     - Block multipliers
--          - asynchronous (Primitive: MULT18X18)
--          - synchronous  (Primitive: MULT18X18S)
--              . clock enable
--              . synchronous reset
--          - up to 17x17 unsigned multiplication per cell
--          - up to 18x18 signed multiplication per cell (two's complement)
--          - two small multipliers fit into a single cell (instanciation only)
--
-- NOTES:
--     - Mapping multipliers into MULT18X18 cells (Synplify default)
--          - signed/unsigned 3x3 and wider multiplication support
--          - wider multiplier descriptions than acceptable range by a single
--            cell are automatically decomposed into different cells.
--     - Mapping multipliers into MULT18X18S cells
--          - no support yet for registered MULT18X18S (target release 7.1)
--          - enable the global optimization switch : "Pipelining"
--          - or apply the "syn_pipeline" attribute to the set of registers 
--             on the output of the multiplier
--     - Mapping multipliers into logic
--          - no particular constraints (often slower than block multiplier
--             implementation)
-- Log file message: (Resource Usage Report section)
--          MULT18X18S      1 use
-----------------------------------------------------------------------------
-- Example: Signed 16 x 16 multiplier with registered outputs
---------------------------------------------------------------------------*/

module mult18x18s (clk, ce, a, b, p);
  input         clk;
  input         ce;
  input  [15:0] a;
  input  [15:0] b;
  output [31:0] p;

  reg [31:0] p /* synthesis syn_pipeline=1 */;
   // Available in version 7.1
   // value: "false" disable pipelining (default)
   // value: "true" enable pipelining;
  wire   [31:0] p_temp /* synthesis syn_multstyle = "block_mult" */ ;
   // value: "block_mult" force MULT18X18 Virtex-II block multipliers (default)
   // value: "logic"      disable multiplier mapping to MULT18X18 cells

  always @(posedge clk)
  begin
    if (ce == 1'b1)
      p <= p_temp ;
  end

  assign p_temp = a * b;

endmodule