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library verilog; use verilog.vl_types.all; entity mult_gen_v4_0 is generic( bram_addr_width : integer := 8; c_a_type : integer := 0; c_a_width : integer := 16;

library verilog; use verilog.vl_types.all; entity lfsr_v1_0 is generic( c_ainit_val : string := "11111111"; c_enable_rlocs : integer := 0; c_gate : integer :

library verilog; use verilog.vl_types.all; entity vfft32_pkg_v2_0 is port( b_input_width : in vl_logic; w_width : in vl_logic; a_value : in vl

library verilog; use verilog.vl_types.all; entity fifosyncvht is generic( address_width : integer := 8; create_rlocs_for_tbufs: integer := 1; depth : integer :=

library verilog; use verilog.vl_types.all; entity romrvht is generic( address_width : integer := 8; create_rlocs_for_tbufs: integer := 0; data_width : integer := 8;

library verilog; use verilog.vl_types.all; entity hdl_demo is port( rst : in vl_logic; clk : in vl_logic; start_value : in vl_logic_

# # sample NMAKE makefile to make libvpi.dll with VisualC++ on Windows # see windows.txt for more details. # SOURCES = \ # vpi_utilities_test.c \ # list_pathout_ports_vpi.c

# # sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows # CDS_INST_DIR=c:/progra~1/cds SOURCES = \ list_pathout_ports_acc.c \ port

# # sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows # CDS_INST_DIR=c:/progra~1/cds SOURCES = \ invoke_commands_acc.c \ list_ne

# # sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows # CDS_INST_DIR=c:/progra~1/cds SOURCES = \ # sci_alu_combinational_acc.c \ #