_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_pkg_v2_0 is
    port(
        b_input_width   : in     vl_logic;
        w_width         : in     vl_logic;
        a_value         : in     vl_logic;
        b_value         : in     vl_logic
    );
end vfft32_pkg_v2_0;