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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity spi_top is
generic(
max1 : integer := 8;
max2 : integer := 8;
st0 : integer := 0;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_clkdlle is
generic(
clkdv_divide : real := 2.000000;
duty_cycle_correction: string := "TRUE";
factory_jf : i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity x_clkdll is
generic(
clkdv_divide : real := 2.000000;
duty_cycle_correction: string := "TRUE";
factory_jf : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity acc2svht is
generic(
input_width : integer := 8
);
port(
l : in vl_logic;
b :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vfft32_phase_factors_v2_0 is
generic(
w_width : integer := 16
);
port(
clk : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult_gen_v3_1 is
generic(
bram_addr_width : integer := 8;
c_a_type : integer := 0;
c_a_width : integer := 3;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult_gen_v3_0 is
generic(
bram_addr_width : integer := 8;
c_a_type : integer := 0;
c_a_width : integer := 3;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand_fd_v2 is
generic(
init_val : string := "0";
c_enable_rlocs : integer := 1;
no : integer := 0;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dpramvht is
generic(
address_width : integer := 8;
create_rlocs_for_tbufs: integer := 0;
data_width : integer := 8;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vfft32_mem_address_v2_0 is
generic(
points_power : integer := 5;
memory_configuration: integer := 3;
init_value :