_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity acc2svht is
    generic(
        input_width     : integer := 8
    );
    port(
        l               : in     vl_logic;
        b               : in     vl_logic_vector;
        ce              : in     vl_logic;
        c               : in     vl_logic;
        ci              : in     vl_logic;
        s               : out    vl_logic_vector
    );
end acc2svht;