_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_mem_address_v2_0 is
    generic(
        points_power    : integer := 5;
        memory_configuration: integer := 3;
        init_value      : string  := "00000";
        usr_ld_init_value: string  := "00000";
        init_value_1    : string  := "00";
        count_by_value  : string  := "00001";
        count_by_value_1: string  := "01";
        thresh_0_value  : string  := "11111";
        thresh_0_value_dms: string  := "11111";
        two_string      : string  := "10";
        two_string_thresh0: string  := "10"
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        mwr             : in     vl_logic;
        io_pulse        : in     vl_logic;
        io              : in     vl_logic;
        address         : out    vl_logic_vector;
        rank_number     : out    vl_logic_vector(1 downto 0);
        user_ld_addr    : out    vl_logic_vector;
        busy_usr_loading_addr: out    vl_logic;
        initial_data_load_x: out    vl_logic
    );
end vfft32_mem_address_v2_0;