_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity x_clkdlle is
    generic(
        clkdv_divide    : real    := 2.000000;
        duty_cycle_correction: string  := "TRUE";
        factory_jf      : integer := 0;
        maxperclkin     : integer := 100000;
        startup_wait    : string  := "FALSE"
    );
    port(
        clk0            : out    vl_logic;
        clk90           : out    vl_logic;
        clk180          : out    vl_logic;
        clk270          : out    vl_logic;
        clk2x           : out    vl_logic;
        clk2x180        : out    vl_logic;
        clkdv           : out    vl_logic;
        locked          : out    vl_logic;
        clkin           : in     vl_logic;
        clkfb           : in     vl_logic;
        rst             : in     vl_logic
    );
end x_clkdlle;