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_info
m255
13
cModel Technology
dE:\TL_verilog_final\TL_AUTO_SYN_BPSK
vbit_stat
IGLE58cTCdmiebGSQV2PLg3
V@4e
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode12 is
port(
code_out : out vl_logic;
code_clk_out : out vl_logic;
dclkm4 : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode34 is
port(
code_out : out vl_logic;
code_clk_out : out vl_logic;
dclkm4 : in vl_logic;
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
input_generator.v
//
// Verilog Module dwt_final_lib.input_generator.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 11:33:55 03/29/2008
//
// using Mentor Graphics HDL Designer(TM) 20
fixed2int.v
//
// Verilog Module dwt_final_lib.fixed2int.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 15:20:39 05/03/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b
run_xst.cmd
identification
status
time short
memory on
run -ifn run_xst.prj -ifmt VERILOG -ofn pcim_top -p v300bg432-6 -keep_hierarchy yes -equivalent_register_removal no -max_fanout 65535