_primary.vhd

采用匹配滤波

library verilog;
use verilog.vl_types.all;
entity encode12 is
    port(
        code_out        : out    vl_logic;
        code_clk_out    : out    vl_logic;
        dclkm4          : in     vl_logic;
        en_numb         : in     vl_logic_vector(4 downto 0);
        datain          : in     vl_logic;
        reset           : in     vl_logic;
        qufan           : in     vl_logic
    );
end encode12;