fixed2int.v

来自「it is used to find traffic」· Verilog 代码 · 共 33 行

//
// Verilog Module dwt_final_lib.fixed2int.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 15:20:39 05/03/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module fixed2int(fixed_in,int_out);
  input [23:0] fixed_in;
  output [7:0] int_out;
  reg [7:0] int_out;
  
  always@(fixed_in)
  begin
    int_out[7]   <= fixed_in[23];
    if(fixed_in[23]==1'b0)
    begin
    int_out[6:0]<={3'b0,fixed_in[22:16]};
    end
    else
    begin
    int_out[6:0]<={~(fixed_in[22:16])+1'b1};
    end
  end


// ### Please start your Verilog code here ###
endmodule