input_generator.v

来自「it is used to find traffic」· Verilog 代码 · 共 24 行

//
// Verilog Module dwt_final_lib.input_generator.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 11:33:55 03/29/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module input_generator(clock,reset,even_out,odd_out);
  input clock,reset;
  output [7:0] even_out,odd_out;
  reg [7:0] even_out,odd_out;
  
  reg [7:0] [1023:0] ram;
  
  


// ### Please start your Verilog code here ###
endmodule