代码搜索结果
找到约 10,000 项符合
Verilog 的代码
display_driver.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
makefile
#!/usr/bin/gmake -f
# COPYRIGHT (C) 2004 Eklectic Ally, Inc.---------------------------{{{#
# See EKLECTIC_LICENSE for information on legal usage of this file. #
# ----------------------------------
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_control_interface is
port(
clk : in vl_logic;
reset_n : in vl_logic;
cmd : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity TotalSystemController is
generic(
S_RST : integer := 1;
S_WaitforHead : integer := 2;
S_ShiftRegBusy : intege
_info
m255
cModel Technology
dC:\Verilog\chap7\ch7_ex
vi2c_slave
IN;FPBU=PGNDdj[AfLX[AW0
VJ93biMY9lGQ_C8Z@F=azO1
w1107808329
Fi2c_slave.v
L0 6
OE;L;5.8;17
r1
31
vtop
IO4ahOV67O3ERKYSFG`UB20
Ve:gFW1CKLAXc^T:
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity i2c_slave is
port(
scl : in vl_logic;
sda_i : in vl_logic;
sda_oe : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity main_s is
generic(
s0 : integer := 0;
s1 : integer := 1;
s2 : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_clshift is
generic(
lpm_width : integer := 1;
lpm_widthdist : integer := 1;
lpm_shifttype : string := "LOGI
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_fifo is
generic(
lpm_width : integer := 1;
lpm_widthu : integer := 1;
lpm_numwords : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity dds is
port(
clk : in vl_logic;
rst : in vl_logic;
sin_out : out vl_logic_vecto