_primary.vhd

来自「用Verilog 实现将比特流数据转化为SPI协议数据的适配器」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity TotalSystemController is
    generic(
        S_RST           : integer := 1;
        S_WaitforHead   : integer := 2;
        S_ShiftRegBusy  : integer := 4;
        S_Delay01       : integer := 8;
        S_ShiftCONTDecision: integer := 16;
        S_ShiftCONTAdd  : integer := 32;
        S_TailDecision  : integer := 64;
        S_SPIStart      : integer := 128;
        S_IDLE          : integer := 256
    );
    port(
        Clock50MHz      : in     vl_logic;
        SampleCLK       : in     vl_logic;
        RST             : in     vl_logic;
        BarkerFlag      : in     vl_logic;
        TailFlag        : in     vl_logic;
        SPICONTRST      : out    vl_logic;
        S_WforH_Flag    : out    vl_logic
    );
end TotalSystemController;