display_driver.map.qmsg

电子闹钟：基于fpga的电子闹钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 05 11:51:42 2008 " "Info: Processing started: Sun Oct 05 11:51:42 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off display_driver -c display_driver " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off display_driver -c display_driver" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display_driver.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file display_driver.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 p_alarm " "Info: Found design unit 1: p_alarm" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 display_driver-behav " "Info: Found design unit 2: display_driver-behav" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 37 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display_driver " "Info: Found entity 1: display_driver" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 28 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "display_driver " "Info: Elaborating entity \"display_driver\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "display_time display_driver.vhd(40) " "Warning (10631): VHDL Process Statement warning at display_driver.vhd(40): inferring latch(es) for signal or variable \"display_time\", which holds its previous value in one or more paths through the process" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[0\]\[0\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[0\]\[0\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[0\]\[1\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[0\]\[1\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[0\]\[2\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[0\]\[2\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[0\]\[3\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[0\]\[3\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[1\]\[0\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[1\]\[0\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[1\]\[1\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[1\]\[1\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[1\]\[2\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[1\]\[2\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[1\]\[3\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[1\]\[3\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[2\]\[0\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[2\]\[0\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[2\]\[1\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[2\]\[1\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[2\]\[2\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[2\]\[2\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[2\]\[3\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[2\]\[3\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[3\]\[0\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[3\]\[0\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[3\]\[1\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[3\]\[1\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[3\]\[2\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[3\]\[2\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "display_time\[3\]\[3\] display_driver.vhd(40) " "Info (10041): Verilog HDL or VHDL info at display_driver.vhd(40): inferred latch for \"display_time\[3\]\[3\]\"" {  } { { "display_driver.vhd" "" { Text "E:/SOPClab/digital_system_design/alarm_system/display_driver/display_driver.vhd" 40 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "150 " "Info: Implemented 150 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "50 " "Info: Implemented 50 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "29 " "Info: Implemented 29 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "71 " "Info: Implemented 71 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 05 11:51:44 2008 " "Info: Processing ended: Sun Oct 05 11:51:44 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}