代码搜索结果

library verilog; use verilog.vl_types.all; entity dds1 is port( data_fre : in vl_logic_vector(15 downto 0); data_pha : in vl_logic_vector(15 downto 0);

library verilog; use verilog.vl_types.all; entity dds4 is port( data_fre1 : in vl_logic_vector(15 downto 0); data_fre2 : in vl_logic_vector(15 downto 0);

library verilog; use verilog.vl_types.all; entity b_task is port( clk_2_5m : in vl_logic; rst : in vl_logic; nd_b : in vl_logic;

本书简要介绍了<mark>Verilog</mark>硬件描述语言的基础知识，包括语言的基本内容和基本结构 ，以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例，帮助读者掌握语言本身和建模方法，对实际数字系统设计也很有帮助。本书是<mark>Verilog</mark> HDL的初级读本，适用于作为计算机、电子、电气及自控等专业相关课程的教材，也可供有关的科研人员作为参考书。 ...

library verilog; use verilog.vl_types.all; entity cic1s2 is generic( sample : integer := 1; zero : integer := 0 ); port( clk : in

library verilog; use verilog.vl_types.all; entity data_memory is port( clk : in vl_logic; reset : in vl_logic; write_en : in vl_log

library verilog; use verilog.vl_types.all; entity decode is port( clk : in vl_logic; reset : in vl_logic; jmp_en : in vl_logic;

verilog res_acs.v res_stage.v MS_res_ACS1_0.v MS_res_ACS1_1.v MS_res_ACS2_0.v \ MS_res_ACS2_1.v MS_res_stage.v backtrack.v \ acs1_0.v acs1_1.v acs2_0.v acs2_1.v stage.v block.v decoder

verilog res_acs.v res_stage.v MS_res_ACS1_0.v MS_res_ACS1_1.v MS_res_ACS2_0.v \ MS_res_ACS2_1.v MS_res_stage.v backtrack.v \ acs1_0.v acs1_1.v acs2_0.v acs2_1.v stage.v block.v decoder

verilog res_acs.v res_stage.v MS_res_ACS1_0.v MS_res_ACS1_1.v MS_res_ACS2_0.v \ MS_res_ACS2_1.v MS_res_stage.v backtrack.v \ acs1_0.v acs1_1.v acs2_0.v acs2_1.v stage.v block.v decoder