_primary.vhd

来自「单级CIC2倍内插滤波器」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity cic1s2 is
    generic(
        sample          : integer := 1;
        zero            : integer := 0
    );
    port(
        clk             : in     vl_logic;
        data_in         : in     vl_logic_vector(11 downto 0);
        data_out        : out    vl_logic_vector(11 downto 0)
    );
end cic1s2;