_primary.vhd

Verilog编程

library verilog;
use verilog.vl_types.all;
entity dds1 is
    port(
        data_fre        : in     vl_logic_vector(15 downto 0);
        data_pha        : in     vl_logic_vector(15 downto 0);
        pha_acc         : in     vl_logic_vector(15 downto 0);
        we              : in     vl_logic;
        clk             : in     vl_logic;
        sclr            : in     vl_logic;
        rst             : in     vl_logic;
        sine            : out    vl_logic_vector(10 downto 0)
    );
end dds1;