代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_add is
generic(
width_a : integer := 32;
width_b : integer := 32;
width_o : integer := 32;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_ram_io is
generic(
lpm_type : string := "lpm_ram_io";
lpm_width : integer := 1;
lpm_widthad : intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mf_ram7x20_syn is
generic(
ram_width : integer := 20
);
port(
wclk : in vl_logic;
rst_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_bus_mux is
generic(
width_a : integer := 6;
width_b : integer := 6;
width_o : integer := 6
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity parallel_add is
generic(
width : integer := 4;
size : integer := 2;
widthr : integer := 4;
vstest.tbw
version 3
D:/Xilinx/basys/VGAVGA/vs_hs.v
vs_hs
VERILOG
VERILOG
vstest.xwv
Clocked
-
-
1000000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
20000000
20000000
0
0
0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity SPI_Master is
port(
miso : in vl_logic;
mosi : out vl_logic;
sclk : out vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fft_test is
port(
clk : in vl_logic;
reset : in vl_logic;
xn_re : out vl_logic_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity PtoS is
port(
PR_CLK : out vl_logic;
PR_DATA : out vl_logic;
CLK : in vl_logic;