📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity fft_test is port( clk : in vl_logic; reset : in vl_logic; xn_re : out vl_logic_vector(15 downto 0); xn_im : in vl_logic_vector(15 downto 0); xn_index : out vl_logic_vector(6 downto 0); ram_addr : out vl_logic_vector(6 downto 0); rfd : out vl_logic; xk_re : out vl_logic_vector(15 downto 0); xk_im : out vl_logic_vector(15 downto 0); blk : out vl_logic_vector(4 downto 0); start : in vl_logic; done : out vl_logic; xk_index : out vl_logic_vector(6 downto 0) );end fft_test;
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