vstest.tbw

利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序

version 3
D:/Xilinx/basys/VGAVGA/vs_hs.v
vs_hs
VERILOG
VERILOG
vstest.xwv
Clocked
-
-
1000000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
20000000
20000000
0
0
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
counths
clk
countvs
clk
hs
clk
rst
clk
vs
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
counths_DIFF
countvs_DIFF
hs_DIFF
vs_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
rst
hs
vs
counths
countvs
SIGNAL_ORDER_END
-X-X-X-