_primary.vhd

来自「一个关于热敏打印机时序的仿真程序,能够应用于大多数的热敏打印机中,实现了打印数据」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity PtoS is
    port(
        PR_CLK          : out    vl_logic;
        PR_DATA         : out    vl_logic;
        CLK             : in     vl_logic;
        DATA_CS         : in     vl_logic;
        DATA_LATCH      : in     vl_logic;
        DATA            : in     vl_logic_vector(7 downto 0)
    );
end PtoS;