paralla to serials.v.bak

来自「一个关于热敏打印机时序的仿真程序,能够应用于大多数的热敏打印机中,实现了打印数据」· BAK 代码 · 共 71 行

`timescale 1ns/1ns

module PtoS(
               //output
               PR_CLK,
               PR_DATA,
               //input
               CLK,
               DATA_CS,
               DATA_LATCH,
               DATA
           );

output PR_CLK;
output PR_DATA;

input  CLK;
input  DATA_CS;
input  DATA_LATCH;
input  [7:0] DATA;//input 8 bit data

wire   PR_CLK; //the gate control clk
wire   PR_DATA;//the serials data to output

reg    [1:0] flag = 0;
reg    [7:0] d; //the memory that store the input data
reg    [3:0] count = 0;//note: this will be a problem in synthesis

assign PR_CLK  = ((count >= 0) && (count <= 7) && (DATA_CS))? CLK : 1'b0;
assign PR_DATA = (DATA_CS)? d[7] : 1'b0;

always @(posedge CLK)
begin
    if(count == 7)
    begin
        count <= 0;
        if(DATA_CS) 
        begin   
            if(count < 7)
            begin
                if(flag == 0)
                begin
                    count <= 0;
                    flag  <= 1;
                end
                else
                    count <= count + 1;
            end
            if(flag == 1)
                flag <= 2;
        end
    end    
end

always @(posedge DATA_LATCH)
    d = DATA;

always @(posedge PR_CLK)
begin
    if(count == 0)
    begin
        if(flag == 1)
            d <= {d[6:0],1'b0};
        else
            d <= d;
    end
    else if(count <= 7)
        d <= {d[6:0],1'b0};
end

endmodule