test.v

来自「一个关于热敏打印机时序的仿真程序,能够应用于大多数的热敏打印机中,实现了打印数据」· Verilog 代码 · 共 79 行

`timescale 1ns/1ns

module test;

reg       clk;
reg       CS;
reg       LATCH;
reg [3:0] count;
reg [7:0] data_array [0:7];

wire      SCK;
wire      SDATA;
wire [7:0] DATA;

//instanes
PtoS u0(
            .PR_CLK(SCK),
            .PR_DATA(SDATA),
            .CLK(clk),
            .DATA_CS(CS),
            .DATA_LATCH(LATCH),
            .DATA(DATA)
       );

//test code begin
initial 
begin
    clk = 'b0;
    count = 0;
    forever #5 clk = ~clk;
end

initial 
begin
     #5 CS = 'b0;
     forever #80 CS = ~CS;
end 

initial
begin
    LATCH = 'b0;
    #5 LATCH = 'b1;
    #15 LATCH = 'b0;
end

initial 
begin
     data_array[0] = 8'b01010101;
     data_array[1] = 8'b00001111;
     data_array[2] = 8'b10101010;
     data_array[3] = 8'b11110000;
     data_array[4] = 8'b00110011;
     data_array[5] = 8'b10011001;
     data_array[6] = 8'b01100110;
     data_array[7] = 8'b11001100;
end 

always @(posedge CS)
begin
    if(count < 7)
        count <= count + 1;
    else if(count == 7)
        count <= 0;    
end

always @(negedge CS)
begin
    LATCH = 'b1;
    #10  LATCH = 'b0;
end

initial
begin
     #1600 $stop;
end

assign DATA = data_array[count];

endmodule