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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity clk4 is
port(
clkin_in : in vl_logic;
clkin_ibufg_out : out vl_logic;
clk0_out : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity BarkerCodeDecision is
generic(
S_WaitforAdder : integer := 1;
S_DotheAddition : integer := 2;
S_BarkerDecision: integer :
lamp.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity slave_control is
port(
ck : in vl_logic;
reset : in vl_logic;
cs : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity MasterRead is
port(
ck : in vl_logic;
reset : in vl_logic;
start : in vl_logi
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Bwrite_s is
generic(
s0 : integer := 0;
s1 : integer := 1;
s2 : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity control_interface is
port(
CLK : in vl_logic;
RESET_N : in vl_logic;
CMD : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity config_s is
generic(
s0 : integer := 0;
s1 : integer := 1;
s2 : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Bread_s is
generic(
s0 : integer := 0;
s1 : integer := 1;
s2 : integer := 2;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_ram_dp is
generic(
lpm_width : integer := 1;
lpm_widthad : integer := 1;
lpm_indata : string := "REGIS